Decision feedback equalization employing a lookup table

ABSTRACT

A decision feedback equalizer includes a lookup table device. The lookup table device may include a shift register and memory, or may include multiple shift registers and memories. Near-end crosstalk may be reduced using a lookup table device. Echo in a bi-directional port circuit may also be reduced using a lookup table device.

[0001] This application is a divisional of U.S. patent application Ser.No. 10/131,444, filed Apr. 24, 2002, which is incorporated herein byreference.

FIELD

[0002] This document pertains in general to circuits that equalizenon-ideal communications channels, and in particular to circuits thatperform an equalization process to reduce inter-symbol interference whendetecting transmitted symbols.

BACKGROUND

[0003] Integrated circuits typically communicate with one another andwith other devices using conductive transmission lines. The conductivetransmission lines may take the form of traces on a printed wiringboard, cables, or the like. Integrated circuits typically includeinterface circuits that include drivers and receivers coupled to theconductive transmission lines. For example, an interface circuit mayhave a signal driver to drive electrical signals on one transmissionline, and a signal receiver to receive different electrical signals froma second transmission line. Also for example, an interface circuit mayhave both a signal driver and a signal receiver coupled to the sametransmission line for bi-directional communication using a singletransmission line.

[0004] Interface circuits transmit digital bits, or “symbols,” onconductive transmission lines. A symbol may represent one or moredigital bits of information. As the speed of communication increases,the symbols are transmitted faster, and the time distance betweenadjacent symbols becomes smaller. Signal drivers transmit symbols onconductive transmission lines, and signal receivers receive symbols onthe conductive transmission lines.

[0005] An “ideal” transmission line is a transmission line that conductsan electrical signal from one end to the other without distortion. Inpractice, perfectly ideal transmission lines do not exist. As a result,signals that are driven onto one end of conductive transmission linesemerge with varying amounts of distortion at the other end of thetransmission line. As the distortion increases, and the communicationspeed increases, the distortion from one symbol may cause an adjacentsymbol to be received incorrectly. This phenomenon is referred to asinter-symbol interference (ISI).

[0006] To partially alleviate the effects of ISI, a feedback controltechnique known as decision feedback equalization may be used at thesignal receiver. One implementation of this technique converts areceived transmission line analog signal into a digital received signalusing a very fast analog-to-digital converter. A digital feedback signalis subtracted from the digital received signal to compensate for thedistortion caused by the non-ideal transmission line. The digitalfeedback signal is typically created by an “equalizer” that models thetransmission line, and predicts the correct digital feedback signal to“equalize” the distortion, and reduce ISI.

[0007] The feedback control technique just described can consume asignificant amount of circuit resources and power. For example, veryfast analog-to-digital converters can consume significant space andpower, as can the circuits typically used to build equalizers.

[0008] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternate methods and apparatus for reducing inter-symbol interference.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 shows a block diagram of a high speed transmission linkused to explain the various embodiments of the equalization loop andprocess.

[0010]FIG. 2 depicts a block diagram of an embodiment of an equalizationloop.

[0011]FIG. 3 illustrates a symbolic representation of an exemplarydigital filter for use in the equalization loop.

[0012]FIG. 4 shows a lookup table device utilizing a memory device and ashift register.

[0013]FIG. 5 shows a finite impulse response filter utilizing multiplememory devices.

[0014]FIG. 6 depicts a graph showing the relative sizes of differenttypes of equalizer circuits.

[0015]FIG. 7 depicts a circuit schematic of an embodiment of a variableoffset comparator used in an embodiment of the equalization loop.

[0016]FIG. 8 shows a block diagram of another embodiment of a variableoffset comparator.

[0017]FIG. 9 illustrates a block diagram of a high speed transmissionlink featuring a multi-level receiver in which an equalization loop isimplemented.

[0018]FIG. 10 shows an embodiment of an integrated circuit with decisionfeedback equalization combined with echo and near-end crosstalkcancellation.

[0019]FIG. 11 shows another embodiment of an integrated circuit withdecision feedback equalization combined with echo and near-end crosstalkcancellation.

[0020]FIG. 12 shows a pair of periodic pulse signals generated during acalibration procedure for the equalization loop.

[0021]FIG. 13 illustrates a flow diagram of an embodiment of a processfor determining the cursor level used in the equalization loop.

[0022]FIG. 14 shows an embodiment of an electronic system in which acommunication link features the equalization loop.

DESCRIPTION OF EMBODIMENTS

[0023] In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that the variousembodiments of the invention, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein in connection with one embodiment may beimplemented within other embodiments without departing from the spiritand scope of the invention. In addition, it is to be understood that thelocation or arrangement of individual elements within each disclosedembodiment may be modified without departing from the spirit and scopeof the invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims, appropriately interpreted, alongwith the full range of equivalents to which the claims are entitled. Inthe drawings, like numerals refer to the same or similar functionalitythroughout the several views.

[0024] An equalization loop and process is described that has thecapability of correctly detecting the transmitted logic values at areceiver, and that may be implemented at a lower cost than theconventional, all digital equalization methodology. FIG. 1 will helpexplain the various embodiments of the equalization loop and process.This figure shows a block diagram of a high speed transmission link thatfeatures a far end driver 104 coupled to a near end receiver 108 via atransmission line 106. An example transmit sequence having the logicvalues {0,0,1,0,0} and timed according to a driver clock period T_(drv)is transmitted onto signal node 112 as a rectangular transmit pulse 110.

[0025] Each of the logic values in the sequence may be mapped to a lowor high signal level (e.g. 0.0 or 5.0 Volts) in the transmit pulse 110,according to the driver clock. Voltage levels discussed here are merelyintended to illustrate the operation of the equalization loop and arenot intended to be limiting. Those of ordinary skill in the artrecognize that a range of signal levels may be used in the operation ofthe equalization loop. From this point forward in this description,analog signal levels are referred to as having values of from zero toten, where zero corresponds to the lowest possible voltage, tencorresponds to the highest possible voltage, and the intermediate valuesrepresent signal levels that fall between the lowest and highestpossible values.

[0026] In addition, the examples of the equalization loop and processdescribed below are compatible with binary communication links in whicheach symbol in the transmitted signal can have one of only two symboliclevels (logic ‘1’ and logic ‘0’). In general, however, they arecompatible with multi-level links. For example, some embodiments utilizea four pulse amplitude modulation (i.e., 4 PAM) link, in which eachsymbol may take one of four symbolic levels (e.g., 0, 1, 2, and 3).

[0027] If transmission line 106 were ideal, then the transmit pulsewould arrive undistorted at an input to receiver 108, after a time delayfor traveling the length of transmission line 106. In this ideal case,the logic values can be recovered at the receiver by feeding theundistorted received pulse (corresponding to pulse 110) to the input ofa comparator (not shown) having a reference level fixed at five (shownat REF in FIG. 1), which corresponds to the midpoint between the low andhigh signal levels. The output of the comparator could then beperiodically latched, according to a receiver clock having a periodT_(rcvr) that may be phase and frequency locked to that of the driverclock period T_(drv) to recover the transmit sequence {0,0,1,0,0}.

[0028] In practical systems, however, the actual analog signal 120received at signal node 122 is distorted, such as in the example shown.This distortion may be due in part to attenuation effects of thepractical transmission line 106. It can be seen that using the fixedreference comparator described in the previous paragraph might yield anincorrect sequence of all zeros at the receiver 108, because the samplecorresponding to the transmitted logic ‘1’ is equal to the referencelevel of five. The sample corresponding to the transmitted symbol isreferred to herein as the “cursor,” and the samples that are non-zerodue to the transmitted symbol, and that follow the cursor, are referredto herein as “post-cursors.”

[0029] According to an embodiment of the invention, the correct sequenceof logic values may be recovered at receiver 108 by initially decreasingthe reference level to 2.5 so that a received logic ‘0’ or logic ‘1’will be substantially equidistant from the reference level. For example,a received logic ‘0’ will have a signal level of zero and the firstreceived logic ‘1’ will have a signal level of five, so an initialreference level of 2.5 allows for proper detection of the first logic‘1’ occurring after a long string of logical ‘0s’ as shown in FIG. 1.After receiving the first logical ‘1’, the reference level may bechanged each clock cycle thereafter in an attempt to maximize the marginbetween the reference level and the possible signal values thatrepresent a transmitted ‘1’ or ‘0.’ For example, on the clock cyclesubsequent to receiving the first logical ‘1’ after a long string ofzeros, a signal value of three (the first post-cursor shown in FIG. 1)will be superimposed on the transmitted data. If a logical ‘0’ istransmitted next, a signal value of three will be present (zero plusthree), and if a logical ‘1’ is transmitted next, a signal value ofeight will be present (five plus three). To maximize the margin betweenthe reference level and the possible signal levels, the reference levelshould be set to 5.5 (halfway between three and eight). Varying thereference level in this manner yields the correct sequence {0,0,1,0,0}for the example shown in FIG. 1.

[0030] Turning now to FIG. 2, an equalization loop embodiment is shownthat can automatically vary the reference level of a comparator tocorrectly recover a generalized transmit sequence. Assuming transmissionline 206 can be modeled as a linear time invariant system, the loop asdescribed below can correctly recover a wide range of transmit sequences(including a random sequence) that are linear combinations of a pulsesequence such as, for example, {0,0,1,0,0}.

[0031]FIG. 2 shows two integrated circuits at 250 and 260. Integratedcircuit 250 includes driver 204, training data circuit 222, andmultiplexor 217. Integrated circuit 260 includes sampler 224, variableoffset comparator (VOC) 214, multiplexor 219, lookup table device 218,and lookup table programming control circuit 220. Driver 204 drivesdifferential transmission lines 206A and 206B, and sampler 224 receivessignals from differential transmission lines 206A and 206B. Differentialtransmission lines 206A and 206B are collectively referred to astransmission line 206.

[0032] Variable offset comparator 214 is shown in FIG. 2 with signalinput nodes 262A and 262B coupled to receive a differential analogsignal from transmission line 206. In other embodiments, VOC 214 has asingle signal input node coupled to receive a single-ended analog signalfrom a transmission line. A differential system may be useful to reducethe systems susceptibility to common-mode noise, and a single-endedsystem may be useful in systems with larger signals that can toleratemore common-mode noise.

[0033] Variable offset comparator 214 compares the level of the receivedanalog signal to a reference level as described above with reference toFIG. 1. According to an embodiment of the equalization loop, VOC 214 hasa substantially variable offset that is controllable to represent thevariable reference level. Varying the reference is performed by changingthe offset of the VOC 214.

[0034] The output of the VOC 214 provides the logic value which, in thecase of a binary communication link, is also considered to be thereceived data as the result of a comparison between the transmissionline analog signal level and the variable reference level. Variousembodiments of VOC 214 are shown in FIGS. 6 and 7, and are describedbelow with reference thereto.

[0035] The equalization loop shown in FIG. 2 further includes lookuptable device 218 with an input coupled to an output node of VOC 214.Lookup table device 218 also includes an output node coupled to digitaloffset control input node 215 of VOC 214. According to variousembodiments, lookup table device 218 utilizes shift registers and memorydevices arranged to logically implement a discrete time filter, such asa digital finite impulse response (FIR) filter. The discrete time filterprovides a multi-bit binary value that changes in response to a sequenceof logic values that form the received data. In this embodiment, thelogic values are provided directly by the output of VOC 214. The digitaloffset control word provided to VOC 214 may be further modified by othermechanisms added to the receiver. In such cases, the lookup table deviceoutput may be added to these other codes to form a resultant offset codevalue.

[0036] The contents of lookup table device 218 influence the offsetapplied to VOC 214 as a function of past received data. In generalterms, these contents correspond to the output of a discrete time filterthat is implemented by lookup table device 218. The appropriate contentsfor lookup table device 218 may be determined by lookup tableprogramming control circuit 220 during a calibration period. During thecalibration period, driver 204 is fed periodic training pulses(generated by training data circuit 222), rather than valid driver data,through multiplexer 217. The transmitted logic value sequence in thetraining pulses is known by the lookup table programming control circuit220.

[0037] During the calibration period, the lookup table programmingcontrol circuit 220 may need to directly control the offset of VOC 214.Multiplexer 219 allows lookup table programming control circuit 220 todirectly control the offset of VOC 214 during the calibration period.With the contents of lookup table device 218 set so that the receiveddata output from VOC 218 matches the known logic values transmitted fromtraining data circuit 222, the loop is ready for normal operation todetect valid driver data. Since the amount of distortion in transmissionline 206 may change over time while the data communication system is inoperation, the calibration period may be repeated to adapt the contentsof the lookup table device to yield improved detection at the receiver.

[0038] In the embodiment of FIG. 2, a sampler unit 224 is coupledbetween the signal input node of VOC 214 and transmission line 206.Sampler unit 224 may be implemented using a sample and hold circuit withan output node to provide a sampling of the transmission line analogsignal level at a particular point in time. Sampler unit 224 may be usedto reduce jitter in the received data. In such an embodiment, samplerunit 224 is clocked by a receiver clock signal (not shown) that may bephase and frequency locked to a driver clock signal (not shown). Inanother embodiment, sampler unit 224 is not used, and the transmissionline analog signal is fed directly to the signal input node of VOC 214.In such a case, VOC 214 or its latched output may be timed by thereceiver clock.

[0039] Referring now to FIG. 3, a symbolic representation of anexemplary digital FIR filter is shown. This FIR can be logicallyimplemented by lookup table device 218 (FIG. 2), albeit with variousperformance and size differences as discussed below. This particularfilter design includes delay element 304 that can store the results of alinear operation on past received data. Use of this particular filterdesign can allow the loop to correctly detect the transmitted sequence{0,0,1,0,0} from the distorted received signal shown in FIG. 1. Thevalues of the filter coefficients are selected to be a₀=5, a₁=3, anda₂=2. These were selected in view of the distortion shown in FIG. 1 andthe fact that, in this embodiment, the filter output directly representsthe offset of VOC 214. Table 1, below, shows the operation of theequalization loop in such a case: TABLE 1 Time Receiver VOC VOC VOCFilter Point Input Offset Comparison Output Output 1 0 2.5 0 − 2.5 =−2.5 0 2.5 2 5 2.5 5 − 2.5 = 2.5   1 5.5 3 3 5.5 3 − 5.5 = −2.5 0 4.5 42 4.5 2 − 4.5 = −2.5 0 2.5 5 0 2.5 0 − 2.5 = −2.5 0 2.5 6 0 2.5 0 − 2.5= −2.5 0 2.5

[0040] Each row in Table 1 above describes an update to the loop madejust after its corresponding time point. The six time points are thoseshown at signal 120 in FIG. 1. It can be seen from Table 1 that theselected filter coefficients cause the VOC output to yield the correctsequence. The difference between the level at the receiver input and theeffective reference level of the VOC is in all cases equal to 2.5. Thisdifference is known as the ‘voltage margin’ at the input to the VOC.This voltage margin as determined from the table is symmetrical, i.e.,the voltage margin is the same for a logic ‘1’ as well as for a logic‘0’ at the VOC input. The voltage margin is a measure of how much noisein the analog transmitted signal can be tolerated by the receiver,before the receiver output yields the wrong symbol value.

[0041] The FIR shown in FIG. 3 further includes multipliers 302 and 306,and adders 310 and 312. Multiplier 302 receives past received data onnode 320 and also receives the coefficient a₂ on node 322. Multiplier302 multiplies the past received data and the coefficient to produce aproduct on node 324. Node 324 is a signal node that includes multiplephysical signal lines, shown as “n” in FIG. 3. Because node 324represents a digital word with a finite number of signal lines, a smallamount of error is introduced due to quantization. The quantizationerror can be reduced by increasing the value of “n;” however, acorresponding increase in area is then consumed by multiplier 302 andadder 310. Multiplier 306 also introduces quantization error. Adders 310and 312 do not contribute quantization error provided that they arelarge enough to not experience any overflow.

[0042] Finite impulse response filter 300 is referred to as a “two tap”filter because two past data samples are used: one is input tomultiplier 302, and one is input to multiplier 306. The past receiveddata on node 320 consists of digital ‘1s’ and ‘0s.’ When the pastreceived data is a ‘0’, a multiplier will produce a value of zero on itsoutput. When the past received data is a ‘1’, the multiplier willproduce a value equal to the corresponding coefficient on its output.For example, when the past received data on node 320 is a ‘0,’ signalnode 324 will have a digital word equal to zero. Also for example, whenthe past received data on node 320 is a ‘1,’ signal node 324 will have adigital value of equal to coefficient a₂.

[0043] Each tap in the finite impulse response filter has a coefficientequal to a sample value in the impulse response. In situations where theimpulse response lasts a long time, it may be advantageous to includemany taps in the filter to perform effective equalization. Increasingthe number of taps, however, can cause quantization from each tap toaccumulate, and result in a large “cumulative quantization error.”Cumulative quantization error occurs because of limited resolution inthe digital words that represent the tap weights in the filter. To takeadvantage of a large number of taps while maintaining small cumulativequantization error, the resolution must be fine enough to measure thesmall post-cursors far away from the cursor. The combination of highresolution and increased number of taps dramatically increases thecomplexity of the system.

[0044]FIG. 4 shows a lookup table device utilizing a memory device and ashift register. Lookup table device 400 is a lookup table devicesuitable for use as lookup table device 218 (FIG. 2). Lookup tabledevice 400 includes shift register 402 and memory device 404. Shiftregister 402 receives data serially on node 410 and outputs data inparallel on nodes 406. Memory device 404 receives the parallel dataoutput from shift register 402 on nodes 406, and produces a digitaloffset control word on nodes 412.

[0045] Lookup table device 400 logically implements an FIR filtersimilar to that shown in FIG. 3. Finite impulse response filter 300(FIG. 3) receives past received data and outputs a digital offsetcontrol word. Lookup table device 400 also receives past received dataand outputs a digital offset control word. In contrast to finite impulseresponse filter 300, however, lookup table device 400 does not exhibitcumulative quantization error as a result of quantization error for eachtap in the filter. Rather than having multiple sources of quantizationerror that sum to create a cumulative quantization error, lookup tabledevice 400 includes the output of memory device 404 as a single sourceof quantization error.

[0046] Shift register 402 can include any number of delay elements, andnodes 406 can include any number of physical signal lines. For example,in some embodiments, shift register 402 includes five delay elements,and nodes 406 include five signal lines. This corresponds to memorydevice 404 having five bits of address information. Also in someembodiments, the digital offset control word on node 412 is five bitswide. This corresponds to memory device 404 storing five bits ofinformation at each address. In embodiments that have nodes 406 equal tofive bits wide, lookup table device 400 corresponds to a five tap FIRfilter. For every additional tap, one additional address bit is added tonode 406, and memory device 404 doubles in size. This is described inmore detail below with reference to FIG. 6.

[0047]FIG. 5 shows a lookup table device utilizing multiple memorydevices. Lookup table device 500 includes shift registers 502, 512, and522, memory devices 504, 514, and 524, and adder 530. Shift registers502, 512, and 522 are cascaded such that the output of one is input tothe next. For example, shift register 512 receives serial data fromshift register 502 on node 508 and outputs serial data to shift register522 on node 518. Each shift register also outputs parallel data to acorresponding memory device. For example, shift register 502 outputsparallel data on node 506 to memory device 504, shift register 512outputs parallel data on node 516 to memory device 514, and shiftregister 522 outputs parallel data on node 526 to memory device 524.Each memory device shown in FIG. 5 receives parallel data and outputs adigital word to adder 530. Adder 530 receives the data output from thevarious memory devices, and sums it to create a digital offset controlword.

[0048] In embodiments represented by FIG. 5, each shift register andmemory device combination can implement a plurality of taps of an FIRfilter. For example, when each of nodes 506, 516, and 526 are three bitswide, each shift register and memory device combination implements threetaps of a nine tap FIR filter. Although the filter includes nine taps,only three sources of quantization error exists. These three sources arethe outputs of memory devices 504, 514, and 524.

[0049] Lookup table device 500 is a “hybrid” device that utilizes someelements from the memory device embodiment of FIG. 4, and some elementsfrom the FIR filter embodiment of FIG. 3. Specifically, each memorydevice implements a group of one or more taps, and an adder sums theoutput of the memory devices.

[0050]FIG. 6 depicts a graph showing the relative sizes of differenttypes of equalizer circuits. Graph 600 shows curves 602 and 604. Curve602 represents the relative size of a lookup table device utilizing asingle memory device, such as lookup table device 400 (FIG. 4). Curve604 shows the relative size of an FIR filter implemented usingmultipliers and adders, such as FIR filter 300 (FIG. 3). As shown bycurve 602, the size of the memory device doubles for each additionaltap. As explained above, this is due to an additional address bit beingadded to the memory device. As shown by curve 604, the size of a finiteimpulse response filter using multipliers and adders increasessubstantially linearly as taps are added. This is because for eachadditional tap, one additional multiplier and one additional adder isused. In practice, curve 604 may not be quite linear, in part because aseach additional tap is added, the size of the additional adder mayincrease.

[0051] The relative size of a nine tap FIR filter is shown at 610. Thecorresponding size of a nine tap filter implemented with a memory devicewould be much larger. The relative size of a three tap filterimplemented with a memory device is shown at 614, and the relative sizeof a nine tap hybrid device such as device 500 (FIG. 5) is shown at 612.As shown in FIG. 6, the nine tap hybrid device has a smaller size thanthe nine tap finite impulse response filter, and as discussed above, hasfewer sources of quantization error.

[0052] The embodiments discussed with reference to FIG. 6 include threetap and nine tap filters. In some embodiments, the relationships betweenthe curves shown are different depending on how the memory devices areimplemented, and how many bits are maintained in the circuits. Forexample, graph 600 shows that the relative sizes of an FIR and a memorydevice would be equal at around six taps. In some embodiments, many moretaps can be used before the size of the memory device equals the size ofthe FIR, and in other embodiments, the sizes are equal at a pointrepresenting fewer than six taps. Many design trade-offs can be madedepending on the importance of size, power, and desired precision.

[0053]FIG. 7 depicts a circuit schematic of an embodiment of a variableoffset comparator (VOC) used in an embodiment of the equalization loop.VOC 700 is a VOC suitable for use as VOC 214 (FIG. 2). VOC 700 includesan amplifier circuit including first and second differential pairs whichare defined by transistors 710, 712, and 720, 722, respectively.Variable current generators 702 and 704 are also coupled to control thetail currents 11 and 12 to the respective differential pairs. Currentgenerators 702 and 704 are controlled by the digital offset control word(see FIG. 2) that is received on multiple signal nodes as shown. In thisembodiment, each digital value of the offset control word corresponds totwo oppositely varying tail currents I₁ and I₂ that are substantiallyequidistant from a nominal tail current. In some embodiments, variablecurrent generators 702 and 704 are implemented using a plurality ofcurrent sources connected in parallel, with each of the current sourcescontrolled by one of the bits in the offset control word. Transistorscan be sized within variable current generators 702 and 704 so that abinary offset control word controls the variable current in a binaryfashion, or so that the current varies linearly with the number of bitsset to a logical ‘1’ in the offset control word.

[0054] A single ended output voltage for this comparator may beavailable as either V_(out) or V_(out)#. To drive these output signalsinto one of two possible stable states, a regenerative load circuit 730is provided as shown. After being reset by an input signal, thisregenerative load circuit 730 quickly amplifies any difference betweenV_(out) and V_(out)# where such amplification occurs at a relativelyhigh gain due to the cross coupled n-channel pair 734 and p-channel pair732, thereby ensuring that the output signals V_(out) and V_(out)# onlyassume one of two possible stable states. Thus, if V_(in) ⁺ is greaterthan V_(in) ⁻ by at least the amount of offset that has been selected(as referred back to the input of the differential pairs), then theregenerative latch circuit 730 forcefully drives V_(out) to a lowvoltage level and simultaneously drives V_(out)# to a high voltagelevel. Other types of regenerative latch circuits may be used to providethe digital output signal.

[0055]FIG. 8 shows a block diagram of another embodiment of a variableoffset comparator (VOC). VOC 800 includes voltage-to-current converter802, current mode digital-to-analog (DAC) converter 804, and currentcomparator 806. Voltage-to-current converter 802 receives analog inputvoltages V_(in) ⁺ and V_(in) ⁻ and produces a differential current oncurrent summing nodes 810 and 812. Current mode DAC 804 receives thedigital offset control word and produces a differential current thatvaries as a function thereof. The currents output fromvoltage-to-current converter 802 and current mode DAC 804 sum on nodes810 and 812, and are input to comparator 806. Comparator 806 comparesthe currents on the current summing nodes and produces a digital output.

[0056]FIG. 9 illustrates a block diagram of a high speed transmissionlink featuring a multi-level receiver in which an equalization loop isimplemented. The multi-level receiver shown in this embodiment includes3 VOCs 914A, 914B, and 914C that are designed to detect the symbols of a4 pulse amplitude modulation (i.e. 4 PAM) link. As in the embodiment ofFIG. 2, a sampler 946 may be provided to help reduce jitter in thereceived data.

[0057] This 4 PAM multi-level receiver may be reference calibrated bymodifying the offsets of the various VOCs while training pulses of knownamplitude are received. Once the three reference levels have beencalibrated, the multi-level receiver may be permitted to detect 4 PAMamplitude modulated data symbols. These symbols are transmitted by afour level driver 940 that is fed by the output of multiplexer (MUX) 944with valid driver data.

[0058] A lookup table device 948 having contents determined by lookuptable programming control circuit is also provided to automaticallycontrol the offset code for each VOC, based on received data provided bya three bit to two bit thermometer encoder 954. A multiplexer 952 isprovided to allow the offset for each VOC 914 to be controlled by eitherthe lookup table device 948 during normal operation, or by the lookuptable programming control circuit 950 during a calibration procedure inwhich the contents of lookup table device 948 are determined.

[0059] Assuming transmission line 206 can be modeled as a linear timeinvariant system, the loop as shown in FIG. 9 can correctly recover awide range of transmit sequences (including a random sequence) that arelinear combinations of a set of pulse sequences such as, for example,{0,0,1,0,0} {0,0,2,0,0} and {0,0,3,0,0}.

[0060] During a calibration period, driver 940 is fed periodic trainingpulses, rather than valid driver data, through MUX 944. During thecalibration period, lookup table programming control unit 950 maydirectly control the offset of each VOC 914. In some embodiments, a bankof lookup table devices (as part of lookup table device 948) are coupledto control the variable offset of each VOC 914 so that a generalizedsequence of multi-bit symbols may be accurately detected in the presenceof distortion caused by travel through transmission line 206.

[0061]FIG. 10 shows an embodiment of an integrated circuit with decisionfeedback equalization combined with echo and near-end crosstalkcancellation. Integrated circuit 1000 includes variable offsetcomparator (VOC) 1014, drivers 1016 and 1018, lookup table devices 1020,1022, and 1024, and adder 1030. Driver 1016 and VOC 1014 combine tocreate a simultaneous bi-directional data port coupled to transmissionline 1002. As previously described, lookup table device 1024 receivespast received data on node 1004 and produces an offset control word onnode 1006. This control word contributes to digital offset control wordon node 1008 to equalize the effects of distortion caused bytransmission line 1002. In addition to offset control information onnode 1006, adder 1030 receives offset control information from lookuptable devices 1020 and 1022. Offset control information received fromlookup table 1020 is received on near-end crosstalk node 1040, andoffset control information received from lookup table device 1022 isreceived on echo cancellation node 1042.

[0062] Driver 1018 is referred to herein as a near-end driver. Near-enddriver 1018 may be a driver located in close physical proximity to VOC1014, such that crosstalk occurs. For example, as outbound data on node1060 causes near-end driver 1018 to drive data on transmission line1062, crosstalk may occur that further distorts any signals received byVOC 1014. Lookup table device 1020 includes offset control informationthat models the effects of this crosstalk so that distortion caused bythe crosstalk can be subtracted using the digital offset control word.Similar to driver 1018 causing crosstalk, driver 1016 may cause echoesthat appear as distortion to VOC 1014. Lookup table device 1022 includesoffset control information to subtract the effects of echo caused bydriver 1016.

[0063] Nodes 1003 and 1063 are “interface nodes” that are electricallyaccessible from both inside and outside the integrated circuit. Forexample, driver 1016 and VOC 1014 access interface node 1003 from insidethe integrated circuit, and transmission line 1002 accesses interfacenode 1003 from outside the integrated circuit.

[0064] For clarity, lookup table programming control circuits have beenomitted from FIG. 10. In some embodiments, separate lookup tableprogramming control circuits exist for each of lookup table devices1020, 1022, and 1024, and in some embodiments a single lookup tableprogramming control circuit is utilized for all three lookup tabledevices.

[0065]FIG. 11 shows another embodiment of an integrated circuit withdecision feedback equalization combined with echo and near-end crosstalkcancellation. Integrated circuit 1100 includes VOC 1014 that receives adigital offset control word to reduce the effects of distortion causedby a non-ideal transmission line, near-end crosstalk, and echo.Integrated circuit 1100 differs from integrated circuit 1000 in themanner in which the digital offset control word is generated. Ratherthan having three separate memory devices and an adder, integratedcircuit 1100 includes shift registers (SR) 1104, 1106, and 1108, andmemory device 1102. Each of shift registers 1104, 1106, and 1108 canhave any number of delay elements, and memory device 1102 can be ofarbitrary size.

[0066] In the above described embodiments, it has been assumed that thereceiver can generate correctly positioned periodic time points, one ofwhich being referred to as the “cursor” as shown in FIG. 12. Inaddition, to determine the lookup table contents, knowledge of thesignal level values at the cursor as well as at the post- andpre-cursors may be needed (see FIG. 12). Accordingly, FIG. 13illustrates a flow diagram of an embodiment of a process for digitizinga received pulse that is being periodically repeated, for determiningthe cursor, post-cursor, and pre-cursor (if any) levels.

[0067] Referring to FIG. 13 and to the periodic training pulses as partof a pulse signal 1204 shown in FIG. 12, the system can be designed sothat the receiver is aware that periodic pulses, rather than validdriver data, are being received. The periodic pulses are sufficientlyspaced apart in time to allow the transmission line to settle (e.g., toallow reflections of a pulse to die out) before each subsequent pulse istransmitted. An analog to digital (A/D) conversion is performed on aninitial sample point, having a non-zero signal level, of a trainingpulse (operation 1304). This may be done by the receiver itself, usingthe VOC as connected in FIG. 2, according to a successive approximationA/D converter process. Alternatively, other A/D conversion proceduresmay be used, including those that are performed by a dedicated, off-chipintegrated circuit test system rather than an on-chip A/D conversiontechnique in the receiver. The process continues with operation 1308.

[0068] In operation 1308, a shift is performed to an adjacent samplepoint of the training pulse. A number of possible sampling points areillustrated at 1206 in FIG. 12. The spacing should be small enough sothat the pulse is sufficiently digitized to yield useful signal levels.After shifting to the adjacent sample point, the A/D conversion isrepeated for that new sample point (operation 1312). Operations 1308 and1312 are repeated until the entire training pulse has been digitized(operation 1316). One way to decide when the entire pulse has beendigitized is when the digitized signal level of the pulse has returnedto its initial value computed in operation 1304.

[0069] Once the pulse has been digitized in its entirety, the cursor maybe determined as follows (operation 1320). For example, the time pointhaving the maximum (absolute value) digitized level in the receivedtraining pulse may be selected to be the cursor. Alternatively, thecursor may be selected as the time point at which the followingrelationship is satisfied for the digitized pulse: maximum of

cursor level−{3|precursor levels|+3|postcursor levels|}

[0070] A cursor selected according to this relationship is also known asan eye-opening of the particular receiver. Note that the cursor computedusing the above relationship is not necessarily the same as the timepoint at which the signal level of the pulse is at its maximum. Othertechniques for determining the cursor may be possible. For example, insome embodiments, statistical processing is performed on the digitizedpulse data over a number of pulses to obtain a better estimate of thecursor location.

[0071] Once the cursor has been selected for the training pulse, thepost-cursors and pre-cursors (if any) can also be readily identifiedbased on a receiver clock period T_(rcvr) (see FIG. 12, pulse 1204).According to an embodiment, these values can also be used to compute thecontents of a lookup table device. The values of the cursor andpost-cursors correspond to the coefficients of the digital FIR filtershown in FIG. 3, where a₀=the cursor level, a₁=the first post-cursorlevel, and a₂=the second post-cursor level.

[0072] Note that the pulse 120 shown in FIG. 1 is referred to as onethat only has post-cursor ISI, because the pre-cursor signal levels arezero. The above-described embodiments may also be used to correctlydetect received pulses that have pre-cursor ISI as well, namely those inwhich the pre-cursor signal levels are non-zero. If pre-cursor ISI isexpected in the received signal, e.g., if the signal level at the firsttime point in the pulse 120 were non-zero, then the a₀ coefficient ofthe digital FIR filter may be modified so that the correct logic value(in this example, 0) is still detected.

[0073] According to an embodiment, once the cursor has been determinedduring the calibration period, the phase of the receiver clock isre-adjusted according to the cursor and then is locked to that of thedriver clock. In addition, once the calibration period is over, thedriver clock should not drastically change its phase or frequency priorto starting the transmission of valid data, if doing so might throw thereceiver clock out of lock. Other techniques for clocking the receiverand the driver are possible.

[0074]FIG. 14 shows an embodiment of an electronic system in which acommunication link features the equalization loop described above. Thesystem has a multi-layer printed wiring board 1404 on which a parallelbus 1408 is formed. The bus 1408 may be of the point-to-point variety,or a multi-drop bus such as those used in a main memory. An integratedcircuit (IC) chip package 1406 is operatively installed on the board tocommunicate using the parallel bus 1408. The installation of the package1406 may be done by a surface mount technique or via a connector orsocket. The package has an IC chip 1410 that includes a logic functionsection, and an input/output (I/O) section as an interface between thelogic function section and the bus 1408. The logic function section maybe one of the following well-known devices: a microprocessor, a memorycontroller, and a bus bridge. Alternatively, other devices that can beimplemented in the logic function section of an IC chip may be used. TheI/O section has a bus receiver in which an equalization loop asdescribed above is provided.

[0075] A second IC package 1412 is also installed on the board 1404 tocommunicate with the first package 1406 via the bus 1408. The second ICpackage 1412 also includes a chip 1414 having an I/O section in which abus receiver is provided to interface the bus 1408, and its own logicfunction section (here shown as a memory controller).

[0076] According to an embodiment, the I/O interfaces of the two chips1410 and 1414 communicate with each other bi-directionally, that isusing the same conductive lines of the bus for both transmitting andreceiving data. Thus, in such an embodiment, drivers are provided, inboth IC chips, that are connected to the same conductive lines of thebus 1408. Other system applications of the equalization loop arepossible, including, for example, a cable receiver.

[0077] It is to be understood that the above description is intended tobe illustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reading and understanding theabove description. The scope of the invention should, therefore, bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

What is claimed is:
 1. An integrated circuit, including: an interfacenode electrically accessible from inside and outside the integratedcircuit; a receiver having an input node coupled to the interface node;and a decision feedback equalizer that includes a lookup table devicecoupled to receive data output from the receiver, wherein the receiveris configured to be responsive to a digital control word generated bythe decision feedback equalizer.
 2. The integrated circuit of claim 1,wherein the receiver comprises a variable offset comparator having avariable offset responsive to the digital control word.
 3. Theintegrated circuit of claim 1, wherein the lookup table device includes:a shift register to receive data output from the receiver; and a memorydevice to receive an output from the shift register and to provide thedigital control word.
 4. The integrated circuit of claim 1, furtherincluding: a driver having an output node coupled to the interface node;and a signal path from the driver to the decision feedback equalizer toreduce the effects of echo contributed by the driver.
 5. The integratedcircuit of claim 4, further including: a training data circuit coupledto an input of the driver to drive a training data sequence on theinterface node.
 6. The integrated circuit of claim 1 further including alookup table programming control circuit to program data into the lookuptable device.
 7. The integrated circuit of claim 1, wherein the decisionfeedback equalizer includes a finite impulse response filter including:a first shift register having a first parallel output node; a secondshift register having a second parallel output node; a first memorydevice responsive to the first parallel output node; and a second memorydevice responsive to the second parallel output node.
 8. An electronicsystem, including: a first integrated circuit including a driver havingan input node and a training data circuit to conditionally drive theinput node of the driver with training data; a signal conductor coupledto an output node of the driver in the first integrated circuit; and asecond integrated circuit including a receiver coupled to the signalconductor, the receiver having a variable offset comparator and adecision feedback equalizer, the decision feedback equalizer including alookup table to apply a digital offset control word to the variableoffset comparator and a circuit to fill the lookup table responsive tothe training data.
 9. The electronic system of claim 8, wherein thedecision feedback equalizer includes a shift register to receive datafrom an output node of the variable offset comparator, and wherein thelookup table is coupled between parallel output nodes of the shiftregister and a digital offset control input node of the variable offsetcomparator.
 10. The electronic system of claim 8, wherein the secondintegrated circuit includes a driver having an output node coupled tothe signal conductor.
 11. The electronic system of claim 10, wherein thedecision feedback equalizer is responsively coupled to data valuestransmitted by the driver in the second integrated circuit to reduce theeffects of echo caused by the driver in the second integrated circuit.12. The electronic system of claim 11, wherein the decision feedbackequalizer includes: a first shift register to receive data from anoutput node of the variable offset comparator; and a second shiftregister to receive the data values transmitted by the driver in thesecond integrated circuit, wherein the lookup table is coupled betweenparallel output nodes of the first and second shift registers and adigital offset control input node of the variable offset comparator. 13.The electronic system of claim 8, further including: a second signalconductor coupled between the first and second integrated circuits; anda driver in the second integrated circuit having an output node coupledto the second signal conductor, wherein the decision feedback equalizeris responsively coupled to data values transmitted by the driver in thesecond integrated circuit to reduce the effects of near-end crosstalkcaused by the driver in the second integrated circuit.
 14. Theelectronic system of claim 13, wherein the decision feedback equalizerincludes: a first shift register coupled to receive data from an outputnode of the variable offset comparator; and a second shift registercoupled to receive the data values transmitted by the driver in thesecond integrated circuit, wherein the lookup table is coupled betweenparallel output nodes of the first and second shift registers and adigital offset control input node of the variable offset comparator. 15.The electronic system of claim 8, wherein the decision feedbackequalizer includes: a first shift register having a first paralleloutput node and a serial output node; a second shift register having aserial input node coupled to the serial output node of the first shiftregister, and having a second parallel output node; a first lookup tablecoupled to the first parallel output node; a second lookup table coupledto the second parallel output node; and an adder circuit to apply a sumof digital outputs of the first and second lookup tables to the variableoffset comparator.
 16. A method, including: recovering a sequence oflogic values at a receiver by initially setting a reference level so asto be substantially equidistant from a logic low level and a logic highlevel; and subsequently adjusting the reference level to increase amargin between a signal level associated with a post-cursor of aselected one of the sequence of logic values and a potential signallevel associated with a logic value following the selected one of thesequence of logic values.
 17. The method of claim 16, further including:repeatedly adjusting the reference level to increase the margin betweenthe signal level associated with the post-cursor and the potentialsignal level.
 18. The method of claim 16, wherein subsequently adjustingthe reference level further includes: adjusting the reference level tobe substantially equidistant from the signal level associated with thepost-cursor and the potential signal level.
 19. The method of claim 16,wherein subsequently adjusting the reference level further includes:receiving past received data at a finite impulse response filter;adjusting the reference level responsive to a digital offset controlword provided by the finite impulse response filter.
 20. The method ofclaim 19, wherein the finite impulse response filter includes multipletaps.
 21. The method of claim 16, wherein subsequently adjusting thereference level further includes: accessing a lookup table to adjust thereference level.
 22. The method of claim 21, wherein the lookup table iscoupled to a programming control circuit to control an offset code for avariable offset comparator.